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<grw> anyone tried diskless boot on aarch64?
<grw> seems a nice way to avoid slow mmc i/o
<gchristensen> I've done it on high-end server hw
<grw> on the cavium?
<grw> i think scaleway use it for their armv7 boxes too
<gchristensen> yeah the cavium
<grw> what do you use as target?
<grw> i think my next step is hacking gonbdserver to serve nix-store paths directly :)
<gchristensen> what do you mean as target?
<grw> nbd server
<gchristensen> oh, it is just a ramdisk
<grw> i mean the server software
<gchristensen> it is an ipxe image
<gchristensen> so just http
<grw> ah nice :)
<gchristensen> sorry if I'm not following, I'm a bit of a novice in this area :)
<grw> that would be easier..
<grw> me too, my cluster is total pile of hacks :D
<gchristensen> :)
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<arianvp2> everybody's cluster is a total pile of hacks
<arianvp2> :')
<arianvp2> wait wat. Bazel is written in java?
<arianvp2> :'(
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<samueldr> just bought a discounted Rockchip 3288-C chromebit :)
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<sphalerite> samueldr: woo, same chipset as my chromebook! If you need any guidance on getting nixos running on it feel free to ask me :)
<samueldr> that's partly why
<samueldr> I'll be able to look at the first blocks on the device
<samueldr> see if they too are read-only
<samueldr> I hope also to build a "proper" u-boot for it
<samueldr> I didn't find yet (didn'T look hard enough) information on whether there are uart or serial pads
<sphalerite> So would that be coreboot -> U-boot rather than coreboot -> depthcharge?
<sphalerite> Personally I think it'd be cooler to have coreboot load Linux directly
<samueldr> sure, but I assumed that it was u-boot -> depth charge
<samueldr> I thought chrome* hardware used coreboot only on intel?
* samueldr needs to do some reading
<samueldr> if it's u-boot, though, the infra is already all in nixos :)
<samueldr> ah, it may very well be using coreboot, neat https://github.com/coreboot/coreboot/tree/master/src/soc/rockchip/rk3288
<samueldr> I love how google mandates upstreaming everything with chromeos
<samueldr> ah, if it's like the C201 I'll be pretty safe playing around with coreboot, I just received an SOIC clip recently
<samueldr> clever // someone added clever's binary cache for armv7l on the wiki, I'm assuming this is okay in my edit over the section, but if clever doesn't want it publicized ping me and I'll remove it
<samueldr> (prefixing since I read previously it will only match as a prefix)
<gchristensen> what is it?