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<samueldr> hey, pixel 3 friends, it *looks* like you're going to have the same issue as with razer-cheryl2, wherein the kernel source tree assumes strongly the OS will only enable and use DRM
<samueldr> (the good kind of DRM)
<samueldr> and possibly many recent qualcomm, or other SoCs too, android devices
<samueldr> and it looks like, at a quick glance, they let rot the code for non-DRM framebuffer, which anyway might not have worked
<samueldr> and, the part that is really annoying
<samueldr> they didn't implement the changes to the DRM FBDEV emulation
<samueldr> I tried importing the code from google's kernel into the razer tree, and with a quick look it seems it is the same
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<samueldr> btw I fully expect we'll have to draw up a plan for proper first-class DRM support, especially if we want to have those fancy devices with eDP via type-c working
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<samueldr> neat
<samueldr> I now have a tool to automatically get information from "android dumps" (the project)
<samueldr> right now I can get the kernel config from the OEM and the kernel version number automatically
<samueldr> turns out google's kernels have the config... I just failed at unpacking the kernel, it's lz4 and not gzip compressed
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<samueldr> heywoodlh: according to my unproven heuristics, cheryl (1) shouldn't have issues with plain ol' framebuffer, so whatever I say about razer-cheryl2 probably does not apply to your device
<samueldr> I have taken some notes about DRM-requiring devices here https://github.com/NixOS/mobile-nixos/issues/203
<{^_^}> mobile-nixos#203 (by samueldr, 1 hour ago, open): First-class DRM support *without* fbdev support
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<lovesegfault> srk: Try and see if you can get this to cross-cc https://github.com/lovesegfault/hyperpixel-init
<lovesegfault> Try getting an x86_64 machine to cross that to aarch64
<lovesegfault> if you manage make a PR because I've bene unable to
<lovesegfault> something always explodes
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<clever> lovesegfault: how readable does this look? https://gist.github.com/cleverca22/b602c32228ac9c0a051c37513cdddb50
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* lovesegfault reads
<lovesegfault> clever: going to be posting my notes here:
<lovesegfault> 1. what is a plane
<samueldr> I didn't know 2020 was such a mess that people forgot that planes go brrr in the sky
<lovesegfault> 2. what is "dlist memory"? dlist == display list?
<lovesegfault> samueldr: :D
<clever> lovesegfault: a plane is a single image being rendered on-screen, and the hw can render about ~580 planes at once
<clever> lovesegfault: each is basically a self-contained bitmap image in ram
<clever> the display list (dlist) is then a list of which things to render
<lovesegfault> got it
<lovesegfault> [CTL(valid,...), POS0, POS2, POS3, POINT0, POINTCTX, PITCH0, CTL(END)]
<lovesegfault> This isn't super clear to me
<lovesegfault> so this is a dlist
<clever> you want a control word 0 with the valid bit set (and maybe others)
<clever> then position 0, position 2, position 3, pointer 0, pointer context, pitch 0
<lovesegfault> what's CTL(valid,...)? and why does it skip over POS1?
<clever> lovesegfault: under position 1, "only present when not using unity scaling
<clever> "
<lovesegfault> Oh, I see, it then documents all those
<lovesegfault> > the pitch for each plane
<{^_^}> undefined variable 'the' at (string):324:1
<clever> `CTL(valid,...)` means a control word, with the valid bit set
<lovesegfault> this needs some more explaining :P
<clever> if you have a multi-plane image such as YUV, each plane has its own pointer and pitch word
<clever> exact details are still fuzzy to me
<clever> lovesegfault: in the 2nd file (which is meant to be read first), i also link to https://blog.benjdoherty.com/2019/05/21/Exploring-Hardware-Compositing-With-the-Raspberry-Pi/ which explains the HVS overall
<lovesegfault> Ah, looking at that now
<lovesegfault> What are scanlines?
<clever> a single line of the image, covering the full width of a display
<lovesegfault> got it
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